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The fetch-decode-execute cycle is a key feature of the von Neumann architecture and consists of seven stages:

1. The memory address held in the program counter (PC) is copied into the memory address register (MAR).
2. The address in the program counter is incremented (increased) by one. The program counter now holds the address of the next instruction to be fetched.
3. The processor sends a signal along the address bus to the memory address held in the MAR.
4. The instruction or data held in that memory address is sent along the data bus to the memory data register (MDR).
5. The instruction or data held in the MDR is copied into the current instruction register (CIR).
6. The instruction or data held in the CIR is decoded and then executed. Results of processing are stored in the accumulator (ACC).
7. The cycle returns to step one.